As is well known, increased device density, together with higher speed performance and lower power consumption are major driving forces in improving integrated circuit manufacturing devices and methods. For example, CMOS design considerations for high speed digital applications are usually determined by the pull up time and pull down time of each individual gate. Individual gates are associated with a delay time period for signal propagation in PMOS and NMOS gate electrodes. The delay time period, in turn, is inversely proportional to the drive current (Idrive). It is therefore clear that maximizing the drive current will increase the performance speed or Figure of Merit (FOM) of a CMOS device.
Mechanical stresses are known to play a role in charge carrier mobility which affect several critical parameters including Voltage threshold (VT) shift, drive current saturation (IDsat), and drive current (Idrive). Of particular importance as a measure of the speed of device performance is the value of Ion−Ioff, also referred to as the drive current (Idrive). The effect of locally induced mechanical stresses to strain a MOSFET device channel region and the consequential effect on charge carrier mobility is believed to be influenced by complex physical processes related to acoustic and optical phonon scattering. Ideally, an increase in charge carrier mobility in the channel region of the MOSFET will increase the drive current (Idrive)
Prior art processes have proposed several approaches to inducing strain in a MOSFET channel region. For example, biaxial in-plane tensile strain induced by Si/SiGe lattice mismatch has been successfully introduced for both bulk silicon and silicon on insulator (SOI) CMOS devices. However, several shortcomings are associated with this approach including issues such as cost and process integration issues related to scalability and acceptable manufacture and performance of conventional CMOS device structures such as shallow trench isolation (STI) structures.
Prior art processes have also attempted to introduce mechanical strain into the channel region by forming a stressed (strained) contact etching stop layer over the polysilicon gate structure. In this approach, the degree of strain induced in the channel region is limited by the size of the offset spacer which is dictated by design requirements of source/drain formation. For example the offset spacers act as a buffer between the stressed contact etching stop layer and the channel region, limiting the degree of strain which can be introduced into the channel region.
Another problem with prior art channel stressing techniques include the opposing effects on NMOS and PMOS device performance in introducing localized mechanical stresses to strain a channel region. For example, tensile strain (stress) introduction into the channel region improves NMOS performance while degrading PMOS performance, while compressive stress (strain) has the opposite effect. As a result, unacceptable trade-offs between NMOS and PMOS performance is necessary in prior art channel strain inducing techniques.
One effort in the prior art that has been proposed to overcome the problem of opposite polarity CMOS device degradation include ion implanting the contact etching stop layer overlying the opposite polarity device with Ge ions to relax the stress in the contact etch stop layer (CESL). For example, nitride contact etch stop layers of the prior art have been formed with a relatively high level of tensile stress requiring a high level of ion implantation to selectively relax the tensile stress in the CESL overlying e.g., a PMOS device. As a result, the nitride contact etch stop layer may be severely damaged, which can have the effect of undesirably changing etching rates and causing unintentional overetching in subsequent contact formation processes, for example causing damage to underlying silicon or polysilicon portions of a CMOS device, thereby degrading device performance and reliability.
Other approaches to overcoming the degrading effects of a selected type of mechanical stress on a device of opposite polarity have included selectively implanting the gate electrode with different dopant ions including an overlying high tensile stressed capping layer over the gate electrode to achieve, for example, a compressive stress on annealing the gate electrode of an NMOS or NFET device.
The prior art approaches in general, suffer from manufacturing cost, process integration issues and difficulty in producing acceptable device quality to achieve desired device performance and reliability.
These and other shortcomings demonstrate a continuing need in the MOSFET integrated circuit manufacturing art for improved strained channel MOSFETs and manufacturing methods to reliably and predictably achieve improved device performance while ensuring device reliability.
It is therefore an object of the present invention to provide improved strained channel MOSFETs and manufacturing methods to reliably and predictably achieve improved device performance while ensuring device reliability, in addition to overcoming other shortcomings of the prior art.